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[Embeded-SCM Develop] pci.tar

Description: verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus.
Platform: | Size: 13253632 | Author: yemao | Hits:

[VHDL-FPGA-Verilog] i2c_master_slave_core

Description: I2C master/slave IP core
Platform: | Size: 2180096 | Author: zhanglh | Hits:

[2D Graphic] yavga

Description: This core is a simple and small VGA controller. * It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel clock) * It displays chars on the screen (each char is 8x16 pixels) * It has a customizable charset (you can use a simple text editor in order to "visually" customize it) * It can display a color "waveform" * It can display a color grid and "cross cursor" -This core is a simple and small VGA controller. * It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel clock) * It displays chars on the screen (each char is 8x16 pixels) * It has a customizable charset (you can use a simple text editor in order to "visually" customize it) * It can display a color "waveform" * It can display a color grid and "cross cursor"
Platform: | Size: 44032 | Author: sdroamt | Hits:

[Crack Hack] tripledes

Description: 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
Platform: | Size: 31744 | Author: Yan, Like | Hits:

[VHDL-FPGA-Verilog] RealizationofdigitaldownconversionbyFPGA

Description: 介绍在FPGA 器件上如何实现单通道数字下变频（DDC）系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the preparation of some call a combination of IP core method of the FPGA digital down conversion method, and completed its main modules of simulation and debugging, and initial system-level verification.
Platform: | Size: 162816 | Author: 于银 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ-Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wave, step adjustable. Frequency range 1HZ- 10MHZ
Platform: | Size: 117760 | Author: tiancheng | Hits:

[Crack Hack] aes_core

Description: aes_core verified verilog ip core-aes_core verified verilog ip core
Platform: | Size: 11264 | Author: 邓婕 | Hits:

[Program doc] xge_mac_latest.tar

Description: Language - Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. -Language- Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae.
Platform: | Size: 813056 | Author: Maxim | Hits:

[VHDL-FPGA-Verilog] arm7

Description: ARM7core verilog 源代码-ARM7 core verilog source code
Platform: | Size: 3224576 | Author: gongwen | Hits:

[VHDL-FPGA-Verilog] cpu_four

Description:
Platform: | Size: 40960 | Author: Melody | Hits:

[Software Engineering] i2c.tar

Description: i2c core for verilog hdl
Platform: | Size: 647168 | Author: mona | Hits:

[Software Engineering] i2c_customer_pack

Description: i2c core for verilog hdl
Platform: | Size: 515072 | Author: mona | Hits:

[Post-TeleCom sofeware systems] qam_64

Description: 64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核-64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS
Platform: | Size: 1024 | Author: zhujing | Hits:

[VHDL-FPGA-Verilog] 8051Verilog

Description: 利用FPGA可编程的特点，在内部编写了一个8051单片机软核。已通过调试。-The use of FPGA programmable features, in-house preparation of a 8051 soft-core. Passed debugging.
Platform: | Size: 55296 | Author: ql | Hits:

[Other] altera_nand_controller

Description: Altera合作伙伴Eureka Technology.和Cast Inc.为Altera FPGA芯片定制的Nand flash controller IP core-Altera partner Eureka Technology. And the Cast Inc. For the Altera FPGA chip custom Nand flash controller IP core
Platform: | Size: 296960 | Author: Trevor | Hits:

[VHDL-FPGA-Verilog] Ipcoredesign

Description: 微电子/软硬IP核设计：IP核脚本指南，模型开发指南-Microelectronics/soft and hard IP core design: IP core Scripting Guide, Model Development Guide
Platform: | Size: 581632 | Author: qq | Hits:

[VHDL-FPGA-Verilog] fsk

Description: 用Verilog实现FSK调制，调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine
Platform: | Size: 1024 | Author: Sapphire | Hits:

[VHDL-FPGA-Verilog] wishbone_m4_s8

Description: wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
Platform: | Size: 3072 | Author: mis_hey | Hits:

[ARM-PowerPC-ColdFire-MIPS] arm7verilog

Description: ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
Platform: | Size: 1400832 | Author: zdh | Hits:

[VHDL-FPGA-Verilog] ds18b20s16

Description:
Platform: | Size: 443392 | Author: chenwl | Hits:
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